This invention relates to a semiconductor memory device using MOS transistors of stacked gate structures as memory cells and capable of rewriting/reading out data and more particularly to the technique for replacing a defective cell by a redundancy cell when the defect occurs in a semiconductor memory device for effecting the erasing operation in the block unit.
A memory cell of an EEPROM for electrically erasing/programming data is generally constructed by a MOS transistor (nonvolatile transistor) of stacked gate structure using two-layered polysilicon layers which are isolated from each other by an insulating film as shown in FIG. 1. This type of memory cell is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 27 No. 11 November 1992 pp. 1540-1545.
In the above memory cell, a floating gate 11 is formed of a first-level polysilicon layer and a control gate is formed of a second-level polysilicon layer. A source region 14 and drain region 15 are separately formed in a silicon substrate 13 which lies below the floating gate 11 and control gate 12. An inter-level insulating film 16 is formed on the entire portion of the main surface of the substrate 13 and a contact hole 17 is formed in that portion of the inter-level insulating film 16 which lies on the drain region 15. A data line (bit line) 18 formed of metal such as aluminum is formed on the inter-level insulating film 16 and in the contact hole 17 and electrically connected with the drain region 15.
Next, the data programming, reading and erasing operations in the memory cell of the above structure is explained.
The programming operation is effected by, for example, respectively setting the drain potential VD, control gate potential VCG and source potential VS at 5.0V, 9.0V and 0V and injecting hot electrons into the floating gate 11 to change the threshold voltage.
The erasing operation is effected by, for example, setting the control gate potential VCG at -7.0V, setting the drain into the electrically floating state and setting the source potential VS at 5.0V, for example. In this state, electrons in the floating gate 11 are withdrawn into the source region 14 by the tunnel effect.
The reading operation is effected by, for example, respectively setting the control gate potential VCG, drain potential VD and source potential VS at 4.8V, 0.6V and 0V. At this time, if the memory cell is set in the programmed state, no current flows between the source and drain. Memory data at this time is set as "0". If the memory cell is set in the erased state, a current of approx. 30 .mu.A flows between the source and drain. Memory data at this time is set as "1".
In the memory cell with the above structure, various defects will occur in the manufacturing process due to the lattice defect in the silicon substrate 13 and the defect of the insulating film. For example, it is considered that the silicon substrate 13 will be short-circuited to the floating gate 11 or control gate 12. In this case, it becomes impossible to effect the correct programming, erasing and reading operations. This problem becomes more serious with an increase in the memory capacity of the semiconductor memory device, and particularly, it is important at the starting time of the manufacturing line for performing the fine patterning process.
In order to solve the above problem, various types of redundancy circuits are generally provided in the semiconductor memory device. The redundancy technology is disclosed in, for example, Japanese Patent Application KOKAI Publication No. 11-213691.
FIG. 2 is a block diagram showing the schematic construction of a nonvolatile semiconductor memory device using MOS transistors with the above stacked gate structures as memory cells and having redundancy cells which will be used instead of defective cells. The semiconductor memory device includes a column address buffer 20, column decoder 21, row address buffer 22, R/D (redundancy) address storing section 23, R/D address comparing section 24, block address buffer 25, block cores 26-0 to 26-n, sense amplifier (S/A) 27, input/output buffer 28 and input/output pad 29. Each of the block cores 26-0 to 26-n includes a memory cell array 30, row decoder 31, R/D memory cell array 32, R/D row decoder 33, block decoder 34 and column selection gates CT0 to CTj.
In the memory cell array 30, memory cells having the same structure as shown in FIG. 1 are arranged in a matrix form. The drains of the memory cells on each column are commonly connected to a corresponding one of bit lines BL0 to BLj and the control gates of the memory cells on each row are commonly connected to a corresponding one of word lines WL0 to WLk.
A row address signal ADDRi is input from the exterior to the row address buffer 22 and an output signal ARSi thereof is supplied to the row decoders 31 of the block cores 26-0 to 26-n as an internal row address signal. One of the word lines WL0 to WLk is selected by the row decoder 31. A column address signal ADDCi is input from the exterior to the column address buffer 20. An output signal ACSi of the column address buffer 20 is supplied to and decoded by the column decoder 21 as an internal column address signal and then supplied to the column selection gates CT0 to CTj of each of the block cores 26-0 to 26-n. One of the bit lines BLO to BLj is selected by the column selection gates CT0 to CTj and one memory cell connected to the selected bit line and selected word line is selected.
Stored data of the selected memory cell is supplied to the sense amplifier 27 via the selected column selection gate, amplified and then output to the exterior from the input/output pad 29 via the input/output buffer 28.
Next, a case wherein a memory cell in the memory cell array 30 is defective is considered. In the R/D memory cell array 32 used for replacement of the defective cell, a plurality of memory cells are arranged in a matrix form like the memory cell array 30. In the present device, addresses of the defective portions are previously stored in the R/D address storing section 23. An output signal AFi of the R/D address storing section 23 is compared with an output signal ARSi of the row address buffer 22 in the R/D address comparing section 24. If the result of comparison indicates coincidence of the output signals, a signal HITR is output from the R/D comparing section 24 and supplied to the R/D row decoders 33 of the block cores 26-0 to 26-n. Then, one of the R/D row decoders 33 which corresponds to the memory cell array 30 containing the defective cell is set into the enable state to select one of word lines WLRD-0 to WLRD-I. At this time, one of the row decoders 31 which corresponds to the memory cell array 30 containing the defective cell is forcedly set into the non-selected state by a signal ROWDIS output from the R/D address comparing section 24. The sources of all of the memory cells in the memory cell array 30 and R/D memory cell array 32 are connected to a corresponding one of common source lines SLi (i=0 to n), an output signal of the block decoder 34 is commonly supplied thereto and the erase operation is simultaneously effected at the erasing time (block erasing).
Generally, a plurality of erasing cores (corresponding to the block cores 26-0 to 26-n in FIG. 2) are present in one semiconductor memory device. Next, the erase operation of the present device is explained in detail. A source potential 5.0V is applied from the common source lines SLi (i=0 to n) to the source lines of the memory cells in the memory cell array 30 and R/D memory cell array 32 in each of the block cores 26-0 top 26-n. A potential of -7.0V is applied from the row decoder 31 and R/D row decoder 33 to the word lines WLO to WLk and WLRD-0 to WLRD-I. However, 0V is applied to the defective row of the memory cell array 30 and the unused R/D row of the R/D memory cell array 32. At this time, the substrate potential of all of the memory cells is set at 0V so as to prevent application of stress to the defective cell.
Recently, however, with an increase in the integration density of the semiconductor memory device, the structure itself of the memory cell shown in FIG. 1 becomes a serious problem. That is, since it is extremely important that a variation in the threshold voltage of the memory cell after the erase operation is suppressed to minimum in the erase operation, the source region 14 is relatively deeply formed in the memory cell shown in FIG. 1. At this time, the degree (Xj) of entry of impurity into under the gate becomes large to reduce the effective gate length (Leff). Therefore, it is necessary to determine the control gate length by taking the above fact into consideration and it is necessary to previously set the control gate 12 longer. This is a factor for preventing a reduction in the cell area.
By taking the above fact into consideration, a memory cell of the structure shown in FIG. 3 which is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 27 No. 11 November 1992 pp. 1547-1553 is proposed. In FIG. 3, portions which correspond to those of FIG. 1 are denoted by the same reference numerals. The memory cell is formed in a P-well region 35 formed in the silicon substrate 13. The P-well region 35 is formed in an element isolating N-well region 36.
The programming and reading operations of the memory cell with the above structure are the same as those of the memory cell shown in FIG. 1. In the programming and reading operations, 0V is applied to the N-well region 36 and P-well region 35. The erase operation is effected as follows. That is, for example, the floating gate potential VCG is set at -7.5V, the drain is set in the electrically floating state and 10V is applied to the P-well region 35 and N-well region 36, for example. At this time, the source potential VS is set at 10V (or the source may be set in the electrically floating state). Thus, electrons in the. floating gate 11 are withdrawn into the P-well region 35 by the tunnel effect. At this time, since the erasing process is effected in the facing surfaces of the floating gate 11 and P-well region 35, it is not necessary to form the source region 14 deep and the degree (Xj) of entry of impurity into under the gate can be suppressed. As a result, the cell area can be easily reduced.
Next, a case wherein the memory cell with the above structure is applied to the semiconductor memory device shown in FIG. 2 is considered. At this time, it is assumed that the P-well region 35 and N-well region 36 are commonly connected to the source of each memory cell via the common source line SLi. As described before, in the erase operation, 0V is applied to the defective row and unused R/D row. However, at this time, 10V is applied as the P-well potential which is the substrate potential of the memory cell. For example, if the control gate 12 is short-circuited to the substrate (P-well region 35), the potential of the P-well region 35 is short-circuited via the row decoder 31 and it becomes impossible to apply a correct P-well potential. As a result, there occurs a possibility that the erase operation cannot be effected for the block or the erase operation cannot be effected within a preset period of time.
As described above, in the conventional semiconductor memory device, a problem that it is difficult to reduce the memory cell area occurs although it is possible to replace the defective memory cell in the row unit if the memory cell of the structure in which the high potential is applied to the source to withdraw electrons in the floating gate into the source is used. If the memory cell of the structure in which the high potential is applied to the P-well region used as the substrate to withdraw electrons in the floating gate into the P-well region is used in order to solve the above problem, it becomes easy to reduce the cell area, but there occurs problem that the potential of the P-well region cannot be correctly applied and the erase operation cannot be effected when replacement of the memory cells in the row unit is made.